Majority logic system

ABSTRACT

Each of three redundant multiphase signal generating circuits provides a six phase square wave modulated driving pulse train that is adapted for driving the gates of a number of inverters of a standby power supply system. For each of the six phases of each channel, a simultaneous majority logic is employed to enforce agreement among like phase square waves of the several channels. Each channel operates independently of each other channel but monitors the outputs of the other channels. When and only when an individual channel finds itself in disagreement with two other channels, then such individual channel forces itself into agreement with the others. Thus three redundant six-phase signals are retained if the trigger input to one channel is lost. Even with total loss of one channel, the remaining two will continue normal operation.

United States Patent [1 1 Butler, Jr. Nov. 6, 1973 MAJORITY LOGIC SYSTEM 3,427,474 2/1969 Chua 307/246 [75] Inventor: Luther C. Butler, Jr., Garden Grove, 52: 2:22 Q

Calif [73] Assignee: Lorain Products Corp., Lorain, Ohio Primary Examiner-John W. Huclkert Assistant ExaminerLarry N. Anagnos [22] Filed 1972 Attorney-Gausewitz, Carr & Rothenberg [21] Appl. No.: 244,948

Related US. Application Data [57] ABSTRACT Division of 3,8751 Feb 5, 1970- Each of three redundant multiphase signal generating circuits provides a six phase square wave modulated Cl 307/220 R, 307/234, driving pulse train that is adapted for driving the gates 328/l 10 of a number of inverters ofa standby power supply sysf CL H03k 21/36 tem. For each of the six phases of each channel, a si- Fleld of Search multaneous majority logic is employed to enforce 220 427, agreement among like phase square waves of the sev- 269; 323/41, 58, 110, 111 eral channels. Each channel operates independently of each other channel but monitors the outputs of the 156] References cued other channels. When and only when an individual UNITED STATES PATENTS channel finds itself in disagreement with two other 3,435,258 3/1969 McAvoy 307/234 x Channels, Such individual Channel forces itself into 3,414,735 12/1963 H i et 1, 307 24 X agreement with the others. Thus three redundant six- 2,95l,989 9/1960 Schreiner..... 307/235 X phase signals are retained if the trigger input to one 3,500,369 3/1970 Kellam, Jr 307/234 X channel is lost. Even with total loss of one channel, the

Zlflll at a]. X remaining two continue normal operation 3,182,205 5/1965 Sorrells et al.... 307/214 3,226,570 12/1965 Rosenbaum 307/234 X 7 Claims, 5 Drawing Figures KEG 200 A951, 202 [F --0 4% I92 AM J /90 FQO/ll OZ 6/175 /82 PMHHEDNUY 6 ms lice .1.

SHEET 1 c? s new: czocz GENE EA T0? PHASE CA/AM 1T l/Vl/EETM GATES //Vl 2 TEES PAIENIEBNDV 6 I973 SHEET 3 EF 5 SHEU U BF 5 "H W HID NOV 6 I575 MAJORITY LOGIC SYSTEM Feb. 5, 1970.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to redundant signal generators and more particularly concerns multiphase, multichannel generators of maximized reliability.

2. Description of Prior Art Redundancy of control, information handling, or signal generating has long been employed where maximum reliability is required and where the expense, weight, and bulk of the redundant structures can be tolerated, Optimumly, in such redundant systems, each channel individually should be capable of assuming the entire burden alone. That is, if one or all of a group of the redundant channels of control or signal generation should fail, the desired result still should be available by the use of the remaining channel or channels. With such an arrangement, the failed channel or channels are simply ignored and the system may continue to operate. However, in some systems, as for example, in those where multichannel control signals are employed for driving precision frequency sensitive systems, it is necessary, in addition to obtaining redundancy, to insure synchronization between and amoong the several channels of information. This is necessary in order to obtain a true redundancy wherein information from any channel can be employed together with or in place of information from other channels within loss of frequency or phase. In order to enforce such synchronization in redundant channels, it has been suggested in the past that one channel be employed as a master with the others slaved to synchronism with and from the master channel. In such an arrangement, of course, it is necessary to provide synchronizing control information from the master channel to the slave channel whereby if such interchannel control information would be lost or subject to error one or more of the redundant channels is lost or its accuracy destroyed. A similar drawback exists in those systems wherein some logic circuit outside of all channels looks at all three channels and then enforces a simultaneous synchronization upon all these channels. This use of interchannel control signals severely comprises the relative independence of operation of each of the channels, a mode of operation that is highly desirable in reliable redundant systems. Furthermore, the loss of an interchannel synchronizing signal from, in the one case the master channel, or in an alternate case the external logic circuit, may result in loss of one or more of the channels. Prior systems have introduced additional complexities and added circuitry for majority operation. A basic goal of reliable systems is the minimization of components, circuitry, and length and number of connecting lines, wherefor the simplest majority system is advantageous.

SUMMARY OF THE INVENTION The present invention, in accordance with a preferred embodiment thereof employs a number of channels of bi-stute signal generating circuitry, each being triggered for nominal synchronization of their outputs. In order to ensure synchronization of both phase and frequency among the output signals of the several channels despite the fact that all channels are triggered in synchronism, each channel compares its own output with the outputs of at least two other channels to ascertain synchronism of frequency and phase, However, in order to maintain maximum independence of each channel, no action is taken in any channel except upon ascertaining that the instant channel disagrees with at least two other channels. If, and only if, any one channel finds that its own output disagrees with the outputs of two other channels, then and only then, such individual channel changes its output to conform to the other two channels. With this arrangement, synchronization of phase and frequency of all these channels is maintained with least compromise of independence of operation of any individual channel. No cross-channel control lines are required, and each channel may continue to operate even through another channel has failed. Alternatively, if a channel loses its triggering input, it will take its synchronization from a pair of other operating channels.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram ofa multiphase, multichannel phase generating system according to the present invention,

FIG. 2 is a synchrograph of wave forms produced at the output of one of the channels of FIG. 1 together with signal inputs to such channel.

FIG. 3 illustrates majority logic or interchannel synchronization for one phase of all three channels.

FIG. 4 shows a typical one of the several redundant channels including details of circuitry for generating a six-phase signal and the major synchronizing circuit for such one channel, and

FIG. 5 depicts circuitry of an error detector employed in the described system.

DESCRIPTION OF THE PREFERRED EMBODIMENT General System Although the system of the present invention is applicable to many different situations wherein multichannel redundant multiphase signal generation and control is required, principles of the invention will be described in connection with an embodiment that has been incor porated in anuninterruptible power supply system of the type shown and described in detail in an application of Luther C. Butler, Jr., Thomas W. Grasmehr, and Robert S. .Iamieson for Multichannel Control Circuit filed Feb. 5, 1970, Ser. No. 8877,, now U.S. Pat. No. 3,619,661 which is incorporated by reference herein. Shown and claimed in said application for Multichannel Control Circuit is a system for generating three redundant channels of timing signals that are synchronized in frequency and phase. the present invention embodies a specific mechanization, for bi-state or multiphase signal generators or shift registers, of the invention, or aspects thereof, shown and claimed in said application for Multichannel Control Circuit, and invented jointly by Luther C. Butler, Jr., Thomas W. Grasmehr, and Robert S. Jamieson.

As illustrated in FIG. 1, such a standby, uninterruptible power supply system, includes a group of inverters l0 driven by a number of inverter gates 12 under control of these redundant channels of six phase information provided by a channel I phase generator 14, a channel ll phase generator 16, and a channel Ill phase generator 18. The several phase generator channels are supplied with a train 1,, of inverter gate drive or comb pulses and a train J of timing or clock purses from a drive and clock generator via lines 22 and 24. A third pulse train J* on line 23 is also provided to all channels from the generator 20 for purposes to be described below. Each phase generator channel provides a six phase output to the inverter gates, identified as the plus and minus phases of A, B, and C, respectively, with the output of each channel being also identified by the I, II, or III representing the individual channel.

Many types of circuits for producing fixed repetition rate pulse trains such as the trains J. J*, and J,,, are well known in the art wherefore no detailed description of such pulse generators is necessary. Typical pulse generating circuits of a type that may be employed herein for generating separate sets of comb and clock pulses for each channel are shown and described in the aforesaid application for Multichannel Control Circuit, Ser. No. 8877, now US. Pat. No. 3,619,661.

Although but a single drive and clock pulse generator are described herein for purposes of exposition, in an actual system embodying the present invention each phase generator channel has its own drive and clock pulse generators and these are maintained in synchronism by delayed majority logic circuitry as more particularly described in the aforesaid application for Multichannel Control Circuit.

In this standby power system, and as described in the aforesaid co-pending application, the inverter gates are driven in three-phase operation each by a pair of mutually opposite phase square wave modulated gate drive pulses. Thus it is a function of the embodiment of the invention described herein for purposes of exposition to provide a six-phase square wave modulated pulse train identified as A+, A, B+, B, C+, and C- in FIG. 2. For example, the modulated train of gate drive pulses (herein some times designated as comb pulses) exists or is on from the time identified at r, to t.,, the first half cycle of this modulated signal, and is off for the second half cycle of the signal from t, to At the latter instant, t the modulated signal A+ begins its next cycle. The time instants t, through 1 etc., are con trolled by a train .1 of clock pulses 28 also illustrated in FIG. 2. For use with a six-phase signal that is to be produced at the outputs of each of the three channels illustrated in FIG. 1, the clock pulses 28 have a repetition rate that is six times the repetition rate of the modulating square wave of the gate drive signal A+. For an N phase signal, the train of clock pulses has a repetition rate of N times the repitition rate of the multiphase signal. In other words where, as illustrated in the drawing, one full cycle of a modulated signal of one phase is repeated every 360 degrees, the phase interval between consecutive ones of the clock pulses is 60 degrees. Preferably in the clock pulse train J comprises one pulse 28 for every predetermined intergral number of comb pulses 30 of the train J,,,. The input train J,, of comb pulses is shown in FIG. 2 as comprising a series of negative going pulses 30 of which pulses occurring at each clock pulse are suppressed for reasons to be set forth below. In the embodiment described herein, the comb pulses have a frequency of 14.4 kilohertz, this 360 being selected as integral multiple of a nominal 360 hertz frequency of the clock pulse train J.

It will be seen, as illustrated in FIG. 2, that each modulated comb signal lags the preceding phase modulated comb signal by 60 degrees, that is, by one time interval such as t, t In other words, if the first phase of the modulated signal be considered as A+, the second signal C, is initiated at t and is on until It is then off for the next three time intervals and then on again. So too, the third phase signal B+ is initiated 60 degrees later at time t and remains on for three of the 60 degree intervals. This signal like each of the other is on for degrees and off for 180 degrees. The fourth signal A-- is initiated at time t,,, and as will be noted is of opposite phase with respect to the signal A+. The fifth signal C+ is of opposite phase with respect to the modulated signal C and is initiated at time 1 The last of the six phase signals B- is of opposite phase with respect to the signal 3+ and is initiated at time in the illustration of FIG. 2.

Thus there is required for the inverter gates 12 and inverter 10 of FIG. 1, and concomitantly, there is provided by each of the redundant phase generator channels l4, l6, and 18, the indicated set of six phase signals comprising modulated comb pulses in six phases successively shifted by 60. It will be readily appreciated that a six phase drive is required for a three phase output of the inverters, each of such three phases being displaced by I20 degrees from the others.

As previously indicated, the present invention is concerned with the several channels of phase generators 14, 16 and 18 illustrated FIG. 1. The various gates, inverters, and comb and clock generator 20 are briefly illustrated solely to afford a better understanding of the nature and requirement or the particular phase modulated output of the type illustrated in FIG. 2. Each phase generator channel produces a number of phase control or modulator gate pulses indicated at 32, 34, 36, 38, 40, and 42 in FIG. 2 for the respective phases A+, C, 8+, A, C+, and B- of the modulated signals.

The inverters and gates for which the present plural channel phase generating system is specifically designed require redundant channel multiphase signals, with the singals of the several channels pbeing exactly in phase and at the same frequency as compared to corresponding signals of each of the other channels. Accordingly, each phase generator channel sends out its own output signal to each of the other channels via lines 44, 46, and 48 (FIG. 1). It will be readily understood that although but a single line is shown connecting each channel to the other two channels, the indicated flow of information occurs for each phase of the multiphase signal produced by the channel. This arrangement will be described in greater detail in connection with the detail illustrations of FIG. 4.

The phase generator of each channel normally operates independently of each other in response to the comb and clock signals provided to it directly via lines 22 and 24. Nevertheless, each channel by means of information conveyed on lines 44, 46, and 48 monitors the operation of the other two channels. If, and only if, any one channel, channel II for example, should find that its phase control signal for any of its six phases is not in agreement with the corresponding phase control signal from both of the other channels and such channel, channel I] in this example, will change its phase control pulse of such particular phase in order to conform with the corresponding signals of the other channels. However, should the individual channel find a disagreement with but one of the other channels then no action is taken and the disagreement is ignored.

MAJORITY LOGIC THREE CHANNELS, ONE PHASE Majority synchronizing logic for synchronizing phase and frequency of one phase of the output of all three channels is illustrated in FIG. 3. The several channels for one phase of the signals generated thereby include a channel gate pulse generator 50, 52, and 54, respectively, providing square wave signals, such as that illustrated in FIG. 2 and indicated at 32, to channel modulator gates 56, 58, and 60, respectively. The gate pulse generators are triggered by clock pulses provided on line 24 from the clock generator 20a which forms a part of the drive and clock generator 20 of FIG. 1. Gates 56, 58, and 60 each has a second input thereto from the common line 22 on which appear the comb or inverter gate drive pulses from the drive generator 20b that forms a part of the drive and clock generator 20 of FIG. 1. Each phase generator channel also includes a logic comparator 62, 64, and 66 and an inverting circuit 68, 70 and 72, respectively. Each logic comparator comprises a coincidence gate having first and second inputs thereto from the outputs of the other two channels. The third input to the logic comparator is provided from the output of its own channel via the inverting circuit. Thus, for example, logic comparator 62 of channel I receives as a first input the signal "-32 from channel II, and as a second input the third channel output Ill-32. The third input to logic comparator 62 comprises the inverted version of its own channel output [-32.

The output of each logic comparator is fed back to the input of the corresponding gate pulse generator to effect a change of state of the flip-flop forming part of the generator when the comparator provides an output indicating disagreement of its own channel output with the outputs of two other channels. For. example, if all channels are in synchronism and in phase, logic comparator 62 receives a high input from the signal II-32 and a high input from the third channel signal III-32. Via the inversion circuit 68, it receives a low input from the high channel I signal I-32. Accordingly, the coincidence circuit 62 provides no actuating output. However, should the channel I signal [-32 be lwo when the other two like phase signals are high, the comparator 62 receives three high inputs and thus provides an actu- Thus, the monitoring is inhibited during the clock pulse and for a time sufficient to complete the switching that may occur in response to the clock pulse.

Each of thecomb pulses that occurs in coincidence with one of the clock pulses 28 is suppressed. Suppression of the comb pulse at 360 cycle intervals ensures against the use of possibly weakened inverter gate drive pulse since such pulse, in going through the gate 56, 58, or 60, may be severely attenuated or shortened if it occurs at a time when the modulating square wave comprising the second input to such gate is changing.

DETAILS OF ONE CHANNEL SIX PHASES Illustrated in FIG. 4 are details of one complete channel incuding gate pulse generator and modulator gate together with the logic comparators for each of the six phases of an exemplary channel, channel I. It will be understood that each of the other two channels, channels II and III, is identical in every respect to channel I illustrated in these figures.

The gate pulse generator comprises a conventional shift register known at Johnson or Switch-tail counter including flip-flops or bi-stable multivibrators 74, 76, and 78. The flip-flops are conventional circuits which provide mutually exclusive outputs in any one condition as is well known. Each flip-flop has direct set and rest terminals S and R which, when low, will shift and hold the flip-flop in its set or reset state respecating input to the gate pulse generator to force the generator of this channel into agreement with the other two channels. The operation of the logic comparators 64 and 66 for channels II and III is the same as that described in connection with channel 1 whereby each of these channels II and III continuously monitors the outputs of both of the other channels and when it finds itself to be in-disagreement with both of the other channels forces a change in its own gate pulse generator to enforce agreement between or among all of the channels.

Monitoring action must be inhibited during the time of normal switching in response to clock pulse J although it is desirable to carry out the monitoring as soon as possible after the signal that is to be controlled, if at all, by the monitoring has become true or gone high. Accordingly, each of the logic comparators 62,

64, and 66 has a fourth input via line 23 from the clock generator that momentarily disables the logic comparator during the clock pulse and for an'instant immediately following occurrence of a clock pulse on line 24.

tively providing at the two flip-flop output terminals, respectively, high and low outputs for the best condition of the flip-flop and respectively low and high outputs for the reset condition of the flip-flop. In addition to the direct set and reset terminals responsive to low or negative signals, each flip-flop has a clock input, t, and a set and reset input gate indicated at s and r. Each of the set and reset input gates has two inputs which, when high, enable the input gates and allow the flipflop to be toggled or to change its state when the clock or triggering input goes low. That is, upon the fall of the clock input I, the set of reset gate that is enabled by a high at its two inputs will provide a signal that allows the flip-flop to be set or reset if it is not already in such condition. Thus, the direct set and reset terminals are responsive to steady-state low signals, and the set and reset input gates are enabled by high signals to cause the flip-flop to be toggled on the fall of the clock signal thereto. Typical flip-flops of the type employed in the described system are available as microcircuit ships designated MC945F,G. MC845F,P,G, MC948F,G, MC848F,P,G, described in Integrated Circuit Data Book, First Edition, Aug, 1968, Motorola Semi- Conductor Products, Inc. Thus flip-flop 74 provides at one output terminal the A-phase signal I-38, and at its second output terminal, the opposite phaseA+ signal 1-32. Similarly, flip-flop 76 provides the opposite phase outputs I-40 (C+) and I-34 (C-), and flip-flop 78 provides the opposite phase outputs 142 (B) and I-36 (B+).

The train J of positive clock pulses 28 is provided to each channel at input terminal 68, whence it is fed to each of the set and reset input gates 80, 82 of flip-flop 74. Each of the flip-flops has a simialr pair of reset and set input gates, 84, 86 for flip-flop 76, and 88, 90 for flip-flop 78, and each flip-flop receives as its triggering input clock pulses from the input clock pulse train J. The outputs of each flip-flop are fed. to respectively op posite side input gates of the succeeding flip-flop of this shift register, and the outputs of the final flip-flop 78 are fed back to the same side input gates of the first flip-flop 74, as shown in the drawings. Each of the input gates 80 through 90 of the several flip-flops receives as its second input a feedback signal from the output on the same side of the same flip-flop. With the illustrated connection of these flip-flops, the states of the shift register (at the A+, C-, and B+ outputs) will be as indicated in the following table:

Count FF74 FF76 FF78 It will be seen that the shift register flip-flops assume the indicated series of states for the first six counts of input clock pulses, and then upon the seventh clock pulse, resume the initial state and start counting anew. These states correspond to the flip-flop outputs illustrated in FIG. 2 where the pulse 32, the output of flipflop 74, is true for the first three counts and is false for the next three counts. Phase control pulse 36, the output of flip-flop 78, is false for the first two counts, true for the next three counts, and false for the next two counts. Likewise, phase control pulse 34, the output of flip-flop 76, is false for the first count as illustrated in FIG. 2, true for the next three counts, and false for the next three counts. Each pulse is, of course, true for three counts and false for three counts where each count represents 60degress of a cycle and each signal exists in one state for one half cycle. The opposite phase signals 38, 40, and 42 have states opposite to those indicated in the above table.

In order to prevent the counter from getting into or remaining in its two unused counts, namely, 0 1 O and l 0 l, a NAND gate 91 is provided, having inputs (via connecting leads not shown) from l-38 and [42 of flipflops 74 and 78 and a third input via the illustrated lead from l-34 of flip-flop 76. This gate provides an output to set flip-flop 76 whereby the two unused counts are avoided. NAND 91 and all of the NAND gates illustrated herein are Not AND circuits that provide a low output when all inputs are high and provide a high output when any input is low.

The comb signal, a train of negative going pulses 30 as illustrated in FIG. 2, is fed to each channel at an input terminal 92 and thence inverted in a gate 93 and fed as one input to each of six modulator NAND gates 94, 96, 98, 100, 102, and 104 of the several phases. Each of the six phase control pulse outputs of the three flip-flops is fed as a second input to a different one of the modulator gates 94 thorugh 104, whereby the output of each of these gates, fed through a series of NAND gates 106 through 116 and through a set of emitter follower transistors 118 through 128, provides at channel output terminals 130 through 140 the six phase signals lA+, lA-, lB+, lB- lC+, and lC as illustrated in FIG. 1. Thus the modulated comb signal of FIG. 2 is produced by combining the phase control outputs of the flip-flops with the comb signal in the several modulator gates 94 through 104. An input terminal 142 is employed to suppress the comb signal within the system during startup and shutdown of the inverter system.

In order to provide information for the monitoring of channel I phases by each of the other two channels, each flip-flop output is fed via a pair of inverting buffer circuits or NAND gates 144 and 146, 148 and 150, 152 and 154, 156 and 158, 160 and 162; and 164 and 166, to logic comparators of the other two channels. Thus, for example, the output of flip-flop 74, I-38, is fed to NAND gates 144 and 146 from whence it is sent via lines (not shown in FIG. 4) to each of channels II and II], respectively. Similarly, the other output of flip-flop 74 identified as the signal [-32 is fed via inverting circuits 148 and 150 to the comparator of each of the channels 11 and 111 that compares the phase control pulse signal which is of the same phase as the signal 32.

Just as each output of each flip-flop of the channel I shift register is fed via the indicated inverting circuits to each of the other channels, so to each output of each flip-flop of the shift registers of each other channel is fed to the logic comparison circuits of the channel I phase generator. These logic comparison circuits comprise four input NAND gates through 180, each receiving a first input from the corresponding side of the flip-flop of its own channel, second and third inputs from the inverted outputs of the corresponding side of the corresponding flip-flops of like phase of the other two channels, and a fourth input comprising a momentary disabling signal on line 181 to be described hereinafter.

The inverting buffer gates 144 through 166 feed the state of the several flip-flops in a given channel to the other two channels. The coincidences gates 170 through force majority agreement among the three shift registers. Each of these gates monitors outputs from the other two channels and compares these with the output of its own corresponding flip-flop. lt provides no actuating signal when all agree. Where there is a-unanimous agree in coincidence gate 170, for example, the input from channel 11, the signal indicated as 11-38, and the input from channel III, indicated as Ill-38, are both high, having been inverted by their corresponding output buffer gates, whereas the signal from flip-flop 74, l-38, is low. Thus no switching output. is provided from the coincidence gate 170. If, on the other hand, when the inputs 11-38 and [II-38 are both high, the third input to this gate, the signal l-38, is also high, a disagreement exists. That is, the channel 1 signal is in disagreement with both of the other two channels. In this situation, unless the gate disabling signal appears on line 181, gate 170 provides a negative signal to the direct reset terminal of flip-flop 74 to reset this flip-flop thereby forcing it into agreement with the corresponding flip-flops of the other two channels. This same logic comparison arrangement is repeated for the direct reset input sides of the other two flip-flops 76 and 78 of the channel and is also repeated for all of the direct set terminals of all flip-flops so that majority agreement is enforced upon each of the six phases. The signal on line 181 which is applied as the fourth input to each of the co incidence gates 170 through 180 comprises the train 1* of negative pulses 184 illustrated in FIG. 2. These pulses 184 are produced in synchronism with and of opposite phase relative to the pulses of clock pulse train J. The pulses 184 are, in effect, inverted and stretched versions of the clock pulses. The pulses are stretched (extended in time) by conventional circuitry so that switching of the flip-flop cannot be forced by the majority logic until the flip-flop has had a chance to be switched by the clock pulses J and the circuit has had time to establish a quiescent state.

Accordingly, the clock pulse train J, when it goes low, normally sets or resets each of the three flip-flops into its correct state, that is, causes the flip-flop to change in accordance with the logic provided by the set and reset input gates 80 through 90. If this clock pulse is absent or if a malfunction occurs in the set or reset input gate to the flip-flop, the latter may not have achieved its proper state. In such a situation, the majority action of the coincidence gate acting upon the direct set or direct reset inputs forces agreement. Immediately after the termination of the clock pulse 28 and before the next one of the comb pulses 30 (it will be recalled that the comb pulses occurring in coincidence with clock pulses J have been suppressed), the pulse 184 on line 181 goes high to enable the coincidence gate 170 which then provides a negative going signal to the direct reset input of the flip-flop and forces it into agreement with the corresponding flip-flops of. the other two channels. The pulse train J* is a stretched and inverted version of the clock pulse train. Nevertheless, these pulses are short enough so that the forced agreement will occur before the first comb pulse appears at the input terminal 92.

The enabling pulse train J* is fed via line 181 as the fourth input to each of the coincidence gates 170 through 180 whereby all of the logic comparators act in a substantially similar manner. Accordingly, this phase generator channel may continue to contribute to the production of modulated comb pulses via its output emitter followers even if the clock pulse input thereto is absent or if the input circuits of the several flip-flops fail to operate properly.

ALARM A multiple input OR gate 182 has an input from the outputs of each of the coincidence logic gates 170 through 180, and accordingly, monitors the occurrence of disagreements of this channel with the other two channels. The output of gate 182 is high when any one of its inputs is low. Otherwise, when all inputs are high, this output is low. This will be recognized as the operation of the circuit of the described NAND gates which provides a logical OR function and inversion. lf disagreement occurs upon one or two or three successive ones of clock pulses 28, no action need be taken. However, if the disagreement continues beyond three clock pulses or, if the output of any one of the coincidence gates 170 through 180 is continuously high, an error detector 183 having an input from the output of OR gate 182 will provide an error signal to an alarm flipflop l86which produces an out-of-synchronism alarm for this phase generator channel. By application of a signal at terminal 188, the error flip-flop 186 may be reset.

The error detector circuit 183 (FIG. is a timing or counting-circuit having a parallel resistance capacitance circuit comprising a resistor 190 and a capacitor 191 connected between ground and the input ofa substantially conventional coincidence gate. If a predetermined number, four or more for example, of pulses at the 360 hertz clock rate appear at the output of OR gate 182, capacitor 191 is charged sufficiently to cause the timing circuit 183 to produce an output that sets the error flip-flop, and thus turns in the out-of-synchronization alarm.

As illustrated in FIG. 5, pulses from the output of OR gate 182 are fed to the cathode of'a diode 192 that provides a first of two inputs to the coincidence part of this circuit. The second input is provided from capacitor 191 to a second input diode 194. The common connection of the diode anodes, point 195, is connected via a resistor 196 to a positive potential +V and also to the base of NPN transistor 198 having its collector resistively connected to +V. The emitter of transistor 198 is connected via a diode 200 to the base of a second NPN transistor 202 having its collector resistively connected to +V and its emitter connected to ground. The output of this circuit, at the collector of transistor 202, is connected to trigger the alarm flip-flop 186.

When no out-of-synchronization signal is detected by OR gate 182, the cathode of diode 192 is low, this diode conducts through resistor 196, point 195 is low,

and diode 194 is back biased. Capacitor 191 receives 1 no charge. Upon detection of an out-of-synchronization signal, the output of OR gate 182 goes high, diode 192 is cut off, and diode 194 momentarily conducts through resistor 196 to add an increment of charge to capacitor 191. Point 195 remains below the level at which the normally cut off transistor 198 will conduct. Second and third successive out-of-synchronization signals add second and third charge increments to capacitor 191. The values of circuit components and potentials are so chosen that such a third successive charge increment provides a high signal on the cathode of diode 194 that is substantially equivalent to a logical one for this coincidence circuit. Therefore, if a fourth successive out-of-synchronization signal should occur, both input diodes 192 and 194 are now back biased, point 195 goes high, and transistor 198, normally cut off, conducts. This causes conduction of normally cut off transistor 202 to provide an alarm signal to the flipflop 186. It will be understood that this circuit will also provide an alarm upon occurrence of a continuous high at the cathode of diode 192. Of course, the parameters a may be chosen to cause an alarm upon occurrence of a number of out-of-synchronization signals other than the number four, chosen for purposes of exposition.

To ensure operation of the OR gate 182, pulse lengthening RC networks are incorporated between the direct reset and set lines of each of the three flip-flops and the outputs of logic comparator gates through 180. Thus, for example, on the reset input side of flipflop 74 there is included a resistor 171 connected between the output of gate 170 and the direct reset input to the flip-flop. A capacitor 173 is connected between thisinput and ground. The time constant of this RC network is chosen such that an error signal, a low at the output of gate 170, will be retained for a period of time sufficient to operate and pass through OR gate 182. Each of the other five inputs to the direct set and reset terminals of these three flip-flops have similar RC networks with similarly chosen time constants. This integrating circuit is employed because the flip-flops switch very rapidly and a signal at the output of the comparators may be too short to pass through the OR gate 182.

It will be seen that the circuit of FIG. 5 comprises a pair of unidirectional conducting devices, diodes 192 and 194, forming a coincidence circuit of which a first inputterminal has connected thereto a storage device comprising capacitor 191 and resistor 190. In response to occurrence of a signal at a second input terminal, the cathode of unidirectionally conducting device 192, the circuitry including the supply +V and resistor 196 feed a signal increment through diode 194 to the storage device. When the input signal at the input terminal of the diode 192 has a predetermined characteristic (in the illustrated embodiment, this characteristic is the occurrence of a selected number of out-of-sync pulses from OR gate 182) the signal stored in storage circuit 191, 190 attains a predetermined magnitude so that upon occurrence of the next out-of-synch pulse, the fourth in the exemplary embodiment, there is a coincidence of inputs to the cathodes of both of the diodes 192 and 194. The'reupon, the common output terminal point 195 provides an output signal indicating that the signal of predetermined character has occurred at the input terminal formed by the cathode of unidirectional conducting device 192.

SUMMARY OF THE INVENTION There has been described an improved multiphase redundant signal generator wherein each channel of the multiphase generator has a maximum independence and freedom from each other channel, but nevertheless, monitors each of the others to enforce synchronization of frequency and phase among the channels. If any one channel finds itself in disagreement with both the other channels, it changes to force itself into agreement. However, if the other two channels which are being compared do not agree with each other, no action is taken. Thus each channel may continue to operate even though one of the others suffers from a malfunction, wherefore optimum reliability is attained.

The foregoing detailed description is to be clearly understood as given by way of illustration and example only, the spirit and scope of this invention being limited solely by the appended claims.

I claim:

1. A signal detection circuit comprising an OR gate adapted to receive out of synchronization signals to be detected,

first and second input diodes having first and second input terminals and having output terminals connected in common, said second input terminal being connected to said OR gate to receive said out of synchronization signals,

a switching device having an output terminal and having an input connected to said commonly connected diode output terminals, and

a parallel capacitor-resistor circuit connected to the input terminal of said first diode,

whereby upon occurrence of a signal of predetermined character at the input terminal of the second diode the capacitor will charge sufficiently to provide an input to the first diode.

2. A signal translating circuit comprising a coincidence circuit having first and second input terminals, means responsive to a signal at said first input terminal having a predetermined characteristic for providing an input signal at said second input terminal, said coincidence circuit comprising first and second diodes having first and second input terminals and having output terminals connected in common, said second input terminal being connected to receive an input signal,

a switching device having an output terminal and having an input connected to said commonly connected diode output terminals, and

a parallel capacitor-resistor circuit connected to the input terminal of said first diode,

whereby upon occurrence of a signal of predetermined character at the input terminal of the second diode the capacitor will charge sufficiently to provide an input to the first diode.

3. In a signal translating circuit, in combination,

a coincidence circuit,

a plurality of input terminals in said coincidence circuit, a first one of said input terminals being arranged to receive externally generated signals,

energy storage means for controlling the signal at at least a second of said input terminals in-accordance with the signals at said first input terminal, said energy storage means being adapted to begin storing energy when the signals at first input terminal exceed predetermined levels,

means for connecting said storage means to said second input terminal,

means for draining stored energy from said energy storage means, said coincidence circuit including a plurality of diodes, a switching device, means for connecting a first terminal of each diode to a respective one of the input terminals of said coincidence circuit, means for connecting together the second terminals of said diodes and means for connecting said second diode terminals to said switching means when the first terminals of all diodes assume a predetermined condition.

4. A signal translating circuit for detecting a signal of a predetermined characteristic, said circuit comprising a coincidence circuit including first and second unidirectional conducting devices having first and second input terminals,

an output terminal for producing an output signal on occurrence of a signal of predetermined magnitude at said second input terminal, said first input terminal being adapted to receive an input signal of said predetermined characteristic,

a signal storage device connected to said second I input terminal, and v means including at least one of said unidirectional devices and responsive to occurrence of a signal at said first input terminal for incrementing the signal stored in said storage device and for causing said said stored signal to be incremented so as to attain said predetermined magnitude upon occurrence at said first input terminal of a signal of said predetermined magnitude.

5. The signal translating circuit of claim 4 wherein said means for incrementing the signal stored in the storage device comprises a power supply and a resistor connected in series between the power supply and said first unidirectional conducting device, and wherein said signal storage device comprises a capacitor connected between said power supply and said first unidirectional conducting device.

6. A signal translating circuit for producing an output in response to an input signal of a predetermined character, said circuit comprising a coincidence circuit including first and second unidirectional conducting devices, having first and second input terminals respectively, and

having output terminals connected together to form a circuit output terminal,

a signal storage circuit having an input and output connected with said first input terminal,

means connected with said second unidirectional device and responsive to an input signal at said second input terminal for feeding a signal increment through said first unidirectional device to said storage device for storage therein, whereby said storage device will accumulate a signal of a predetep mined magnitude upon occurrence at said second input terminal of a signal of predetermined character and said coincidence circuit will produce an output at said circuit output terminal in response to coincidence of an input signal at said second input terminal and said signal of predetermined magnitude provided by said storage device at said first input terminal.

7. The signal translating circuit of claim 6 wherein said means connected with said second unidirectional device for feeding a signal increment comprises a power supply and a resistor connected between one side of the power supply and the output terminal of said first unidirectional conducting device, and wherein said storage device comprises a circuit including a capacitor connected between the input terminal of said first uni directional conducting device and the other side of the power supply.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION P t n 982 Dated November 6, 1973 Inventor(s) Luther C. Butler, Jr.

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the specification, column 1, line 15, change the comma, first occurrence, to a period. Column 1, line 27,- change "amoong" to --among--. Column 1, line 31, change "Within" to "Without". Column 2, line 2, change the ,comma, first occurrence, to a period. Column 2, line 15, change "through" to "though- Column 2, line 52, change "the" to -The-. Column 3, line 1, change urses" to --pulses--. Column 3,

line 55, change "intergral to "integral-e. Column 3, line 62, change "360" to "number". Column 4, line 27, after "illustrated" insert --in-. Column 4, 'line 39, chan e "singals" to --s-ignals--. Column 4, line 39, change pbeing" to -being--. Column 5, line 44, change "1W0" to --low--. Column 6, line 16, change "incuding" to -including--.

Column 6, line 28, change "rest" to --reset--. Column 6, line 31, change "best' to --set--. Column 6, line 49, change "ships" to --chips--. Column 6, line 63, change "simialr" to ----similar--. Column 7, line 35, chan e "degress" to --degrees--. Column 7, line 57, change thorugh' to --through Column 8, line 39, change "agree to -agreement--. Column 11, line 11, change "out-of-synch" to '--out-of-'sync-.

Signed and sealed this 16th day of April 1971 (SEAL) Attest:

EDWARD I"I.FLETCHER,JR. C. MARSHALL DANN.

Attesting Officer Commissioner-j of Patents oam PO-IOSO (10-69) USCOMM-DC 6O376-F'69 us, covznnnnn PRINTING ornc: In! o-ass-su. 

1. A signal detection circuit comprising an OR gate adapted to receive out of synchronization signals to be detected, first and second input diodes having first and second input terminals and having output terminals connected in common, said second input terminal being connected to said OR gate to receive said out of synchronization signals, a switching device having an output terminal and having an input connected to said commonly connected diode output terminals, and a parallel capacitor-resistor circuit connected to the input terminal of said first diode, whereby upon occurrence of a signal of predetermined character at the input terminal of the second diode the capacitor will charge sufficiently to provide an input to the first diode.
 2. A signal translating circuit comprising a coincidence circuit having first and second input terminals, means responsive to a signal at said first input terminal having a predetermined characteristic for providing an input signal at said second input terminal, said coincidence circuit comprising first and second diodes having first and second input terminals and having output terminals connected in common, said second input terminal being connected to receive an input signal, a switching device having an output terminal and having an input connected to said commonly connected diode output terminals, and a parallel capacitor-resistor circuit connected to the input terminal of said first diode, whereby upon occurrence of a signal of predetermined character at the input terminal of the second diode the capacitor will charge sufficiently to provide an input to the first diode.
 3. In a signal translating circuit, in combination, a coincidence circuit, a plurality of input terminals in said coincidence circuit, a first one of said input terminals being arranged to receive externally generated signals, energy storage means for controlling the signal at at least a second of said input terminals in accordance with the signals at said first input terminal, said energy storage means being adapted to begin storing energy when the signals at first input terminal exceed predetermined levels, means for connecting said storage means to said second input terminal, means for draining stored energy from said energy storage means, said coincidence circuit including a plurality of diodes, a switching device, means for connecting a first terminal of each diode to a respective one of the input terminals of said coincidence circuit, means for connecting together the second terminals of said diodes and means for connecting said second diode terminals to said switching means when the first terminals of all diodes assume a predetermined condition.
 4. A signal translating circuit for detecting a signal of a predetermined characteristic, said circuit comprising a coincidence circuit including first and second unidirectional conducting devices having first and second input terminals, an output terminal for producing an output signal on occurrence of a signal of predetermined magnitude at said second input terminal, said first input terminal being adapted to receive an input signal of said predetermined characteristic, a signal storage device connected to said second input terminal, and means including at least one of said unidirectional devices and responsive to occurrence of a signal at said first input terminal for incrementing the signal stored in said storage device and for causing said said stored signal to be incremented so as to attain said predetermined magnitude upon occurrence at said first input terminal of a signal of said predetermined magnitude.
 5. The signal translating circuit of claim 4 wherein said means for incrementing the signal stored in the storage device comprises a power supply and a resistor connected in series between the power supply and said first unidirectional conducting device, and wherein said signal storage device comprises a capacitor connected between said power supply and said first unidirectional conducting device.
 6. A signal translating circuit for producing an output in response to an input signal of a predetermined character, said circuit comprising a coincidence circuit including first and second unidirectional conducting devices, having first and second input terminals respectively, and having output terminals connected together to form a circuit output terminal, a signal storage circuit having an input and output connected with said first input terminal, means connected with said second unidirectional device and responsive to an input signal at said second input terminal for feeding a signal increment through said first unidirectional device to said storage device for storage therein, whereby said storage device will accumulate a signal of a predetermined magnitude upon occurrence at said second input terminal of a signal of predetermined character and said coincidence circuit will produce an output at said circuit output terminal in response to coincidence of an input signal at said second input terminal and said signal of predetermined magnitude provided by said storage device at said first input terminal.
 7. The signal translating circuit of claim 6 wherein said means connected with said second unidirectional device for feeding a signal increment comprises a power supply and a resistor connected between one side of the power supply and the output terminal of said first unidirectional conducting device, and wherein said storage device comprises a circuit including a capacitor connected between the input terminal of said first unidirectional conducting device and the other side of the power supply. 